The present invention relates to an apparatus and method for lapping an object edge surface, and more particularly to such apparatus and a method that provide a lapped edge surface that is substantially parallel to a reference line on an integrated circuit (IC) wafer.
Solid state imagers are typically constructed in the form of an IC wafer. For some applications, such as imaging from an earth satellite, it is desired to have about four scanning lines, with each line having about 5000 to 6000 pixels (picture elements) to provide a large field of view with a high resolution. However, a wafer with such a large number of pixels per line is difficult to manufacture with an acceptably low number of defects. Thus wafers having four lines, each line having about 1000 pixels have been made, their edges lapped,and then five or six wafers joined together at the lapped edges to provide the desired 5000 to 6000 pixels per line.
However, these edges must be lapped parallel to the circuitry on the chip with a high degree of accuracy, typically two to five micrometers (.mu.m) across a 0.38 centimeter (cm) wafer edge, so as to be able to be joined to other wafers and form a straightl line array with the spacing between adjacent pixels on adjacent wafers being the same as the spacing between adjacent pixels on the same wafer. Further, the lapping apparatus and method must not excessively chip (cut ) the IC wafer which can create a short circuit that renders the wafer inoperative.
It is therefore desirable to have a lapping apparatus and method that provides a highly accurate lap without excessively chipping the lapped object.